Subsections
Transistor Circuits
Transistor Behavior
The EbersMoll equation describes the relationship between the
collector current and the voltage drop from base to emitter
by

(3) 
where is the reverse leakage current from the emitter to the
base,
C is the elementary unit of charge,
J/K is the Boltzmann constant, and is the
absolute temperature (in Kelvin). With typical doping levels, the
leakage current arising from the ``intrinsic'' behavior of the pure
semiconductor is very small, and the second term () is
negligible, giving a simple exponential dependence of on
.
Figure 13:
A circuit for measuring the current
voltage relationship of an npn junction transistor (for testing the
EbersMoll equation).

 Construct the circuit of Figure 13. The
5 k potentiometer acts as a variable voltage divider allowing
you to vary the voltage across the base emitter junction. The
EbersMoll equation suggests an exponential dependence of the current
flowing from the collector to the emitter on . Measure the
voltage drops across the 100 and 1 k resistors to
deduce and for various values of . Note that
is not the voltage drop from the base to ground in
this circuit. Start with small values of , and do not allow
or to exceed 5 mA.
 Using your data, produce a graph of vs. , and
compare it with the behavior predicted by the EbersMoll equation.
 Use the EbersMoll equation and your data to determine values of
the leakage current and the temperature of your
transistor. Comment on whether you think the EbersMoll equation is a
good model.
 Also use your data to determine an approximate value of
for your transistor. The base current is simply
.
Transistor Switch
Figure 14:
Transistor switch circuit.

The circuit shown in Figure 14 implements a transistor
as a switch controlling power delivered to the ``load'' .
With a proper choice of , closing the mechanical switch drives a
large enough base current that the current flowing through the
collector resistor forces the voltage of the collector below
that of the base. That is, the collector current produces a voltage
drop across of about 5 V. The collector voltage
is very close to the emitter (ground in this case), and the right
branch of the circuit behaves as if the collector is grounded. In this
state, called saturation, increasing the base current can
produce no further increase in the collector current, because ,
not the transistor, is limiting the current. The EbersMoll equation
and the rough rule
do not apply here. Opening
the switch brings below 0.6 V, and the transistor shuts off
power to the load.
In designing the circuit, let us assume that k. (Perhaps we know that this is the resistance of the load
we would like to switch, or perhaps we want to limit the collector
current to
mA.) Within these
constraints, we need to choose an appropriate value of to
produce the behavior outlined above. Assuming for the
transistor, we need a base current of at least 0.05 mA to saturate the
transistor and drive maximal current through . The maximal value
of is then
k. However, it is important to be conservative, because
we cannot depend on a particular value. A transistor operating
in saturation is not sensitive to excess base current, so we can
safely use a base resistor much smaller than our upper limit.
 Construct the circuit of Figure 14 using k and k.
 Verify that the circuit behaves as advertised in the above design
discussion. That is, measure the voltage drops across and
with the switch in ``on'' and ``off'' positions. Also measure the
voltage difference between the collector and emitter in these two
states. Comment on your observations.
Logical NOT Gate
Figure 15:
Logical inverter (NOT gate) circuit.

The circuit of Figure 15 is identical in form to the
switch circuit of Section 3.2, except that we consider
the behavior of the circuit as a logic gate with input and output
terminals labelled with and in the figure. When
is above about 0.6 V, the base current turns on, significant
current flows through , and drops. Conversely, when
drops below 0.6 V, the base and collector currents are zero,
the voltage drop across is zero, and is 5 V. Hence,
this circuit inverts its input, at least in the crude sense that when
is high, is low and vice versa.
 Construct the circuit of Figure 15 using k. Produce a graph of vs. covering
values of in the range 05 V for both k
and k.
 The TTL (TransistorTransistor Logic) digital logic standard
assigns voltages in the range 00.8 V the value 0 or ``false'' and
voltages in the range 2.05 V the value 1 or ``true.'' Drive the
circuit with a square pulse signal alternating between 0 V and 5 V
(not between 2.5 V and +2,5 V). You will need to use the DC offset
knob on the function generator to produce this signal. Based on this
observation and your graph of the transfer function of the circuit,
comment on the extent to which this device behaves like a logical
inverter, or NOT gate, with the truth table:


00.8 V 
``false'' 
2.45 V 
``true'' 
2.05 V 
``true'' 
00.4 V 
``false'' 
Which of the two values of is better for this application? Explain.
 Construct Spice simulations for comparison with your
measurements. You will need to include the following .MODEL
statement for a generic npn bipolar junction transistor (with ) in your circuit file.
.MODEL Qnpn NPN(BF=100)
You can then specify transistors with statements of the form[Name] [C] [B] [E] Qnpn
where the [C], [B], and [E] entries
identify the collector, base, and emitter nodes, respectively.
Common Emitter Amplifier
Transistors are used in amplifiers that amplify voltage and
current. Our first amplifier is a voltage amplifier called a
common emitter amplifier for which a change in input voltage
leads to a change in output voltage
linearly proportional to ,

(4) 
where is a constant called the voltage gain.
Figure 16:
Common emitter amplifier.

Consider the circuit of Figure 16. The values of the
resistors , , , and are chosen so that
is about 7.5 V (centered in the 015 V range) and is about
0.6 V above the emitter, ensuring that a current always flows from the
collector to the emitter, regardless of whether we are exciting the
circuit. This is called the quiescent state, or the
DC operating point, of the circuit.
If we apply a change in voltage to the input,
this change is mirrored by the emitter. To see this, remember that the
transistor is ``on'' and so the emitter voltage stays about 0.6 V
below the base. We have
, leading to a
change in the emitter current
. The
collector and emitter currents are approximately equal, since
, so we find

(5) 
giving a voltage gain of

(6) 
The minus sign comes in, because an increase in current through
lowers the collector voltage.
Note that the behavior of the circuit does not depend on the
value of the transistor. That is, we rely on the fact that the
exponential dependence of on ensures that the
transistor can supply (more than) enough current to follow changes
in the base voltage. An important design consideration is that we must
not saturate the transistor.
Equation 6 might inspire the question ``What happens if
we remove the emitter resistor ? Do we get infinite gain?'' It
turns out that we get maximal gain, but that the intrinsic dynamic
resistance
of the emitterbase junction,
looking at the base from the emitter, limits the gain to a finite
value. Using the EbersMoll equation (Equation 3), we find

(7) 
At room temperature this gives something like
for
in mA and in . In fact, you measured a value of
for your transistor in Section 3.1. If , then the voltage gain becomes

(8) 
which introduces two unwanted visitors  dependence on both
temperature and collector current. The first leads to temperature
instability, and the second leads to nonlinear gain. We avoid these
problems by using a large enough emitter resistor that the
emitter voltage is insensitive to changes in the intrinsic emitter
resistance .
Figure 17:
AC common emitter amplifier with capacitive
coupling on the input and output.

The circuit of Figure 17 includes some refinements over
that of Figure 16. If we only wish to amplify time
dependent signals, we couple the input and output signals to the
circuit with capacitors and . This capacitive coupling removes
DC components from the input and output that might interfere with
the DC operating point of the amplifier. These coupling capacitors
form high pass filters with the input and output impedances. Their
values should be chosen so as to transmit signals of interest. The
capacitor labeled is chosen to bypass the emitter resistor at
signal frequencies. You will investigate the effect this has on the
gain. The bypass capacitor has no effect on the DC behavior of the
circuit.
Note : In making measurements, use the setting
(high impedance) on your oscilloscope probes to minimize loading
effects. Remember to compensate your probes.
 Design the circuit of Figure 16 for a
quiescent collector/emitter current of about 1 mA.^{5}Choose to center the output voltage at 7.5 V. Choose
to limit the effects of the variability of on
the gain to 5%. together with the quiescent set the
emitter voltage. Choose and to place the base 0.6 V above
the emitter. This sets their ratio. Then, choose their absolute values
to strike a balance between the following two competing concerns. First,
we would like the input impedance of the circuit to be as large as
possible. Second, the impedance and present at the base
should be much smaller than the input impedance at the base. This
ensures that the impedance of the ``input source'' is small compared
to that of the load it drives. Stated another way, this ensures that
enough current flows through and to provide needed changes
in base current.
The impedance that and present at the base can be
determined by deactivating the voltage source and determining their
resistance between the base and ground (ignoring the transistor for
the moment). The input impedance of the base looks like viewed
through the base emitter junction. A small change in base current
produces a large change in the emitter current
corresponding to a change in emitter
voltage
. Hence, looking into the
base has in input impedance
.
 Calculate the input and output impedances (in the Thevenin
sense) of your amplifier. Here's a hint for calculating the output
impedance. The impedance looking into the collector is huge,
because the collector draws a fixed current for a given value of
. The transistor acts to maintain this current by changing the
collector voltage by large amounts if necessary. This last sentence
implies a very large collector impedance.
 Check your design work by measuring the DC operating voltages of
the base and emitter. Are the voltages and quiescent currents what you
expect them to be?
 Add coupling capacitors and shown in
Figure 17. Using your input and output impedances,
choose values such that the 3 dB point of the circuit is 100 Hz. Note
that these two high pass filters working together yield a lower
3 dB point for the circuit than they give individually. Measure the
gain as a function of frequency, producing a graph of your results,
and find the 3dB point of the circuit experimentally.
 Add the emitter bypass capacitor to the circuit, and
observe the effects this has on the gain of the circuit as a function
of frequency. That is, produce a gain vs. frequency graph to compare
with your graph without the bypass capacitor.^{6}
 Check the linearity of your amplifier, both with and
without the emitter bypass capacitor, by driving it with a triangle
wave form. Any distortion in the output wave form reveals nonlinear
gain.
Our second amplifier circuit is a current amplifier called an
emitter follower with a linear voltage gain of
approximately one. The output impedance of the circuit is much smaller
than the input impedance, while the voltage level is unchanged.
Hence, instead of amplifying voltage, this circuit amplifies the
current (and power) of the input signal.
Figure 18:
AC emitter follower circuit with capacitive
coupling on the input and output.

Consider the circuit of Figure 18. After working with the
common emitter amplifier you are likely to have developed some
intuition about how to choose values for the resistors
and capacitors in this circuit. As with the common emitter amplifier,
the DC operating point of the circuit will keep the transistor
activated. Changes in base voltage are mirrored at the emitter,
because the emitter stays about 0.6 V below the base when the
transistor is ``on'' and not saturated. Hence
and . ^{7} The value
of the emitter resistor is chosen to center the DC output
voltage at 7.5 V for the desired quiescent collector/emitter
current. The ratio is set to place the base 0.6 V above
the emitter, and the absolute values are set in the same way as for
the the common emitter amplifier (see Section 3.4).
Note : In making measurements, use the setting
(high impedance) on your oscilloscope probes to minimize loading
effects. Remember to compensate your probes.
 Construct the circuit of Figure 18. The first
design step is to decide on a quiescent collector/emitter
current. Without a specific load in mind, an arbitrary choice of
mA will get you started. Choose coupling capacitors
that give a 3 dB point for the circuit of 100 Hz. Note that these
two high pass filters working together yield a lower
3 dB point for the circuit than they give individually.
 Check your design work by measuring the DC operating voltages of
the base and emitter. Are the voltages and quiescent currents what you
expect them to be?
 Determine the input impedance by placing a resistor in series
with the source and measuring the drop in output voltage. (Think
voltage divider.)
 Determine the output impedance by measuring the upper
3 dB point of the circuit using the capacitor as the load (in
parallel with ) rather than as a coupling capacitor.
Typical ``real world'' signals consist of a superposition of a
``noise'' signal and a signal or signals of interest. For example, the
signal at the bottom of Figure 19 shows a
superposition of slow variations of large magnitude as well as faster
variations of smaller magnitude. Let us assume that the slower, larger
signal is our signal of interest. We could try using a high pass
filter to eliminate the smaller, faster signal. However, if we are
only interested in knowing when and for how long our signal of
interest is above some threshold, we could use transistors to produce
a circuit with an output voltage that is high or ``on'' when its input
signal is above a ``turn on'' threshold and low or ``off'' otherwise. This
circuit would produce several very short output pulses due to noise
fluctuations as the signal crossed the threshold. If we refine the
design so that the output only swings low after the signal crosses
a second lower ``turn off'' threshold, we limit the
sensitivity of the circuit to noise. In order for this idea to work,
the difference between our ``turn on'' and ``turn off'' voltage
thresholds should be somewhat larger than the peak to peak magnitude
of the noise as shown in Figure 19.
Figure 19:
A ``noisy'' input signal is shown below
the desired output  high or ``on'' when the input signal has passed a
``turn on'' threshold and has not yet fallen below a lower
``turn off'' threshold. The two thresholds are arranged to prevent the
circuit from responding to fluctuations due to noise.

The device described above is known as a Schmitt trigger. It is an
example of a class of devices called bistable multivibrators
or flip flops. These devices, because they have two possible
output states dependent on the history of the input signal have (at
least short term) memory.
Figure 20:
Nonlinear two state amplifier with
different ``on'' and ``off'' input thresholds called a Schmitt
trigger.

The circuit of Figure 20 is a Schmitt trigger
circuit. The two transistors and are the key to the
bistable behavior of the circuit. With the circuit in the ``on''
state, is active (
V) while is
inactive ( V). In the ``off'' state, they trade
roles. Neither transistor is saturated. It is important to note that
these are not conclusions one can draw looking
Figure 20 in the absence of resistance values. Instead,
these are assertions that get us started in understanding the behavior
of the circuit. It is further helpful to start at the left of
Figure 19 and think through the generation of an
output pulse as follows.
 low, low (trigger ``off'')
The trigger is ``off'' in this state. We start with the assumption
that in this state, is inactive and is active.
If we mentally remove from the circuit as depicted in
Figure 21(a), we have what looks like a somewhat
tangled common emitter amplifier. The base voltage of
is set by the voltage divider consisting of and . If
is active but not saturated,
V, or

(9) 
where is the collector current of . For our purposes, we
can and do consider the collector and emitter currents to be
equal. Further, the output voltage corresponding to the ``off'' state
is given by

(10) 
Figure 21:
Schmitt trigger in the (a) ``off''
( inactive) and (b) ``on'' ( inactive) states.
(a)
(b)

 rising, low (trigger ``off'')
Noting that the emitters of and are tied together, we
conclude that the base and base emitter voltages at which they
activate are equal. We already know the voltage of the base of
when the circuit is in the ``off'' state. Hence, we have the input
threshold for turning on and triggering the transition to the
``on'' state,

(11) 
 high, high (trigger ``on'')
The trigger is in the ``on'' state (see
Figure 21). Once is inactive, ,
and there is no voltage drop across . We can conclude that

(12) 
 falling, high (trigger ``on'')
In this state, there are three unique currents , , and
flowing in the circuit as shown in
Figure 21(b). The node rule gives

(13) 
We can further observe, via the loop rule, that

(14) 
The key to finding the ``turn off''
threshold input voltage is recognizing that the base
emitter voltages of and are both V when
is deactivating and is activating. This yields a third
constraint

(15) 
which, together with Equations 13 and
14 allows us to eliminate the three unknown
currents. In this way, it can be shown that

(16) 
 Use Spice to predict the behavior of the circuit assuming
k, k, k,
k, and k.
You will need to use two separate DC sweep analyses (one from 0 V up
to 5 V, and one from 5 V down to 0 V) instead of a transient
analysis.^{8}Produce a graph of vs. . Make note of the values of
, , , and that Spice
predicts.
 Build the circuit using the resistance values you used in your
Spice simulation, and use the XY mode of the oscilloscope to
produce a graph of vs. for comparison with your
Spice calculation. Measure actual values of ,
, , and . How well do Spice and
experiment compare?
 Use Equations 911
to show that

(17) 
 Fill in the missing steps leading from
Equations 1315 to
Equation 16 in the design discussion
above. Compare theoretical predictions of ,
, , and with your measurements and
Spice results.
 What are the theoretical input and output impedances of the
circuit in terms of the resistances , , , , and
? The voltage specifications of your Schmitt trigger (the values
of , , , and you report)
actually depend on the input and output impedances of your trigger,
the input impedance of the load, and output impedance of the driving
circuit. If you would like your circuit to adhere to these
specifications to within 1%, estimate (a) the upper limit on output
impedances of circuits used to generate input signals for your Schmitt
trigger, and (b) the lower limit on input impedances of loads driven
by your Schmitt trigger. Do the function generator and oscilloscope
you used to evaluate the circuit fall within these limits?
Copyright © 20012004, Lewis A. Riley

Updated Mon Jan 19 13:29:10 2004

This work is licensed under a Creative Commons License.